1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory card having a NAND-type flash memory and the like therein is being downsized and provided with high capacity rapidly. For realization of a downsized memory card, semiconductor elements such as a memory element, a controller element and the like are mounted in a stacked form on a wiring board. The electrode pads of the semiconductor elements are electrically connected to the connection pads of the wiring board by wire bonding. Besides, the memory elements are also stacked into multiple layers on the wiring board to provide a high capacity memory card.
There is a tendency that the number of memory elements stacked is increased. It is being studied to stack the memory elements into four, eight or more layers depending on the storage capacity of the memory card. It is being studied to stack the plural semiconductor elements in a step-like shape to expose the electrode pads of the semiconductor elements having, for example, a single short-side pad structure to perform wire bonding of the multilayered semiconductor elements (memory elements) (see JP-A 2001-217383 (KOKAI), JP-A 2005-302871 (KOKAI)).
A length in the stepped direction becomes long with the increase in the number of stacked semiconductor elements, and an occupied area (projected area of all elements) of the semiconductor elements relative to the wiring board increases. Since the size of the memory card is defined, a pad arrangement region of the wiring board is restricted with the increase in the occupied area of the semiconductor elements. Therefore, it becomes difficult to secure a pad arrangement region which is connected to memory elements and a controller element.